1. Technical Field
The present invention relates generally to power conservation; and more particularly to an embedded processor system with selective power control to an internal device including a non-volatile memory array.
2. Description of Related Art
Power management is an important consideration for electronic devices, particularly more sophisticated battery-powered electronic devices. Examples of such applications include, but are not limited to, mobile handsets, smart phones, personal digital assistants (PDAs), automotive Telematic systems, point of sale (POS) input devices, remote controls, remote sensors, laptop personal computers, and computer peripheral devices. Exemplary computer peripheral devices include, but are not limited to, PCMCIA cards, CF cards, USB dongles, wireless keyboards, wireless pointing devices, wireless mice, wireless trackballs, game controllers and joysticks. Many such devices require processing capabilities and wireless communications and incorporate system-on-chip (SOC) designs or the like. The processing and wireless communication functions consume substantial amounts of power significantly reducing battery life. Designers are faced with the trade-off of providing adequate functionality particularly for devices intended for direct human interface, while minimizing power consumption such as in order to sustain a reasonable battery life.
As SOC designs grow in complexity, it becomes more difficult to achieve very low power consumption. Simple clock gating in very large designs still leaves an integrated circuit (IC) with intrinsic leakage simply due to the physical design of the transistors. Even though this leakage current is very small, the combined effect of hundreds of thousands to millions of transistors can cause a small battery to drain in a short period of time.
Thus, there is a need in the art for power management for SOC and IC designs to maximize battery life.